1. Field of the Invention
Generally, the present invention relates to sophisticated integrated circuits, and, more particularly, to techniques for using material substitution processes to form replacement metal gate electrodes, and for forming self-aligned contacts to semiconductor devices made up of the same.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit elements that substantially determine performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry, including field effect transistors, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions.
In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length, and associated therewith the reduction of channel resistivity and increase of gate resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
For many device technology generations, the gate structures of most transistor elements has comprised silicon-based materials, such as a silicon dioxide and/or silicon oxynitride gate dielectric layer, in combination with a polysilicon gate electrode. However, as the channel length of aggressively scaled transistor elements has become increasingly smaller, many newer generation devices have turned to gate electrode stacks comprising alternative materials in an effort to avoid the short-channel effects which may be associated with the use of traditional silicon-based materials in reduced channel length transistors. For example, in some aggressively scaled transistor elements, which may have channel lengths of 14-32 nm, gate electrode stacks comprising a so-called high-k dielectric/metal gate (HK/MG) configuration have been shown to provide significantly enhanced operational characteristics over the heretofore more commonly used silicon dioxide/polysilicon (SiO/poly) configurations.
Depending on the specific overall device requirements, several different high-k materials—i.e., materials having a dielectric constant, or k-value, of approximately 10 or greater—have been used with varying degrees of success for the gate dielectric layer of an HK/MG gate structure. For example, in some transistor element designs, a high-k gate dielectric layer may include tantalum oxide (Ta2O5), hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), aluminum oxide (Al2O3), hafnium silicates (HfSiOx), and the like. Furthermore, a metal material layer made up of one or more of a plurality of different non-polysilicon metal gate electrode materials may be formed above the high-k gate dielectric layer in HK/MG configurations so as to control the work function of the transistor, which is sometimes referred to as a work-function material, or a work-function material layer. These work-function materials may include, for example, titanium (Ti), titanium nitride (TiN), titanium-aluminum (TiAl), aluminum (Al), aluminum nitride (AlN), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), tantalum silicide (TaSi), and the like.
One conventional processing method that is commonly used for forming high-k/metal gate transistor elements is the so-called “gate last” or “replacement gate” technique, wherein initial device processing steps are performed using a “dummy” gate electrode. The term “dummy” gate electrode refers to a process sequence wherein a gate structure that is formed during an early manufacturing stage does not ultimately form a part of the finished semiconductor device, but is instead removed and replaced with an HK/MG replacement gate electrode during a later manufacturing stage. Typically, a “dummy” gate electrode is based on a conventional semiconductor materials and device processing steps, such as, for example, a polysilicon gate architecture and the like. However, due to the overall aggressive scaling of modern semiconductor devices, a variety of problems may occur during device processing that is based on the so-called replacement metal gate (RMG) technique, which can sometimes lead to device defects and/or reduced device reliability. Some of these problems are illustrated in FIGS. 1a-1h and will now be described in further detail below.
FIG. 1a schematically depicts a semiconductor device 100 during a later stage of device processing based on one illustrative prior art RMG technique. The semiconductor device 100 includes transistor elements 150A, 150B formed in and above a semiconductor layer 102 of a substrate 101. As shown in FIG. 1a, the transistor elements 150A, 150B are made up of, among other things, gate structures 110, each of which may include a dummy gate dielectric layer 104 (such as a silicon dioxide or oxynitride material), a dummy gate electrode 105 (such as amorphous silicon or polysilicon material), and sidewall spacer structures 106 (such as a silicon nitride material). It should be appreciated that, depending on the overall device processing requirements, the sidewall spacer structures 106 may be single spacer elements (as schematically depicted in FIG. 1a), or may include a plurality of spacer elements (not shown), such as liner layers, offset spacers, and the like, which are used as mask layers so as to form source/drain regions 102d have been formed in the semiconductor layer 102 based on implantation techniques well known in the art. Furthermore, a first layer portion 103a of an interlayer dielectric material 103 (see, FIG. 1f), such as a silicon dioxide material and the like, is formed above the source/drain regions 102d of the semiconductor layer 102, surrounding the gate structures 110 so as to electrically isolate the transistor elements 150A, 150B, and thereafter planarized so as to expose the upper surface 105s of the dummy gate electrode 105.
In the manufacturing stage of the RMG technique shown in FIG. 1a, the semiconductor device 100 is exposed to a suitably designed multi-step etch process 130 that is first adapted to selectively remove the dummy gate electrodes 105 from the gate structures 110 relative to the sidewall spacer structures 106 and the dummy gate dielectric layers 104. The etch recipe of the etch process 130 may thereafter be adjusted so as to selectively remove any remaining portion of dummy gate dielectric layers 104 from above the channel regions 102c of the respective transistor elements 150A and 150B, thereby forming gate openings or cavities (not shown) between the sidewall spacer structures 106 and above the channel regions 102c in which replacement metal gate electrodes may be formed during later processing steps.
FIG. 1b schematically depicts the semiconductor device 100 after completion of the etch process 130, and after further processing steps of the prior art RMG technique have been performed. As shown in FIG. 1b, a deposition sequence 131 has been performed to form a layer of high-k dielectric material 107 above both transistor elements 150A, 150B—i.e., above the first layer portion 103a, along the inside of the sidewall structures 106, and above the channel region 102c. Furthermore, the deposition parameters of deposition sequence 131 are adjusted so as to thereafter form a layer of work-function material 108 above the high-k dielectric material 107, thereby forming reduced-sized gate cavities 120 having a gap width 120w and a depth 120d. 
As shown in FIG. 1c, a further material deposition process 132 is then performed so as to deposit a layer of conductive metal 109 above both transistor elements 150A, 150B, and so as to fill the reduced-sized gate cavities 120. In a typical prior art process, the deposition process 132 is, for example, a chemical vapor deposition (CVD) process, and the layer of conductive metal 109 is, for example, aluminum. However, as may be appreciated by those of ordinary skill, as transistor devices are more aggressively scaled, and the critical dimensions of those devices (such as gate length and the like) are decreased, the aspect ratio of the reduced-sized gate cavities 120 (i.e., the ratio of the depth 120d to the gap width 120w) greatly increases. Furthermore, the higher aspect ratio of the reduced-sized gate cavities 120 may substantially increase the likelihood that voids 109v may inadvertently be created in the layer of conductive metal 109 used to fill the reduced-sized gate cavities 120 during the material deposition process 132, which may lead to increased resistivity of the resulting metal gate electrodes, as well as a variation in resistivity within a group of gate electrodes. Moreover, the likelihood that voids 109v may be created in the reduced-sized gate cavities 120 increases when the deposition process 132 a CVD process, and when it is used to form a layer of conductive material 109 that comprises aluminum.
In some prior art processes, the gap-fill capabilities of the deposition process 132 used to form the layer of conductive metal 109 may be enhanced by first forming a thin metal liner, or wetting layer 109w (as shown in FIG. 1d), so as to facilitate a more uniform deposition of the conductive metal 109, thus reducing the likelihood that voids 109v may be formed. In general, the material of the wetting layer 109w may be varied depending on the material used for the layer of conductive metal 109. As noted above, in many conventional RMG techniques, aluminum is used for the layer of conductive metal 109, and the most common material used for a wetting layer 109w with an aluminum conductive metal 109 is titanium. However, depending on the overall device processing parameters and the specific materials used, the materials of the layer of conductive metal 109 and the wetting layer 109w may sometimes combine to form metal alloy regions 109r. Such alloy regions 109r may have an increased resistivity, thereby potentially leading to increased resistivity variations between metal gate electrodes. Furthermore, the presence of the metal alloy regions 109r may also induce a non-uniform planarizing effect during a planarization processes 133, such as a chemical mechanical polishing (CMP) process and the like, that may be used during later processing steps to remove excess material of the replacement metal gate material layers 107, 108 and/or 109. Furthermore, additional voids 109v may even be created as a result of the presence of a metal alloy region 109r at or near the upper surface of the finished metal gate structures 110, which can possibly be physically pulled out of the conductive metal layer 109 during the planarization process 133, as shown in FIG. 1e. 
Another problem associated with at least some of the prior art RMG processes is related to the contact elements that are formed to provide electrical connections between a first metallization layer (M1) of the semiconductor device 100 and the source/drain regions 102d of the transistor elements 150A, 150B. As a result of the continuous and aggressive scaling of transistor elements in the semiconductor industry, limitations on the overall capability of traditional photolithography techniques has generally led to the use borderless or self-aligned source/drain contact elements. However, due to the use of very tight gate electrode pitch dimensions 110p, which can be as little as 60 nm or even less as devices are further scaled down, alignment problems inevitably occur between a photoresist mask 125 that is used to pattern contact via openings 111 in the interlayer dielectric material 103 and the overall pattern or spacing of the replacement gate structures 110. Accordingly, as shown in FIG. 1f, the likelihood that a contact via opening 111 may expose both a source/drain region 102d and one or both of the work-function material 108 and the conductive metal 109 of the gate structures 110 increases greatly, a situation which may lead to the creation of a short between the source/drain region 102d and gate structure 110.
As shown in FIG. 1f, one prior art approach that has been used to address the contact alignment issue described above is to convert the metal in the upper portions 108u and 109u of the work-function material 108 and conductive metal 109, respectively, to dielectric materials by using one or more conventional oxidation, nitridization, and/or fluorination processes prior to completing the interlayer dielectric material 103 by forming a second layer portion 103b above the first layer portion 103a. This dielectric material conversion process serves to create a dielectric insulation layer 110d, thereby preventing an electrical contact from being made to the replacement gate structures 110 when a conductive contact element is eventually formed in the contact via opening 111. However, this approach may have some drawbacks, due to the fact that the typical replacement metal gate electrode stack is made up of multiple layers of different metal materials, each of which may respond differently to the various dielectric conversion processes listed above. For example, oxidation rates and minimum oxidation temperatures may vary between the each of the typical metal gate electrode materials, and it can be difficult to oxidize some materials, such as TiN and TaN, at a low enough temperature that does not significantly impact the overall thermal budget of the semiconductor device 100. Furthermore, some metal materials that may commonly be used for manufacturing metal gate electrodes, such as Ti and Ta, cannot be transformed into dielectric materials by nitridization. Additionally, it may also be difficult to achieve an adequate treatment depth when using fluorination processes, such that an acceptable cap layer thickness can ultimately be obtained.
FIGS. 1g-1i illustrate yet another prior art approach that has sometimes been utilized to address the above-noted contact element alignment issues. As shown in FIG. 1g, an etch process 134 is performed so as to form recesses 110r in the gate structures 110 by removing an upper portion of the work-function material 108 and the conductive metal 109. Thereafter, as shown in FIG. 1h, a dielectric material layer 112, such as, for example, a silicon nitride material and the like, is formed above the semiconductor device 100 so as to fill the recesses 110r, and thereby form cap layers 112a above the replacement gate structures 110. However, as illustrated in FIG. 1g, obtaining a uniform recess depth is problematic, again due to the presence of multiple layers of different metal materials, each having differing etch rate characteristics. Furthermore, the overall poor etch selectivity of the various metal gate electrode materials relative to the material of the first layer portion 103a of the interlayer dielectric material 103 may lead to an undesirable over-etching of the first layer portion 103a, thereby also forming undesirable recesses 103r in the first layer portion 103a. In such cases, it will also be necessary to form the dielectric cap layer 112 so as to fill the recesses 103r in the over-etched portions of the first layer portion 103a. 
The dielectric cap layer 112 is then planarized, and the second layer portion 103b is formed above the dielectric cap layer 112b so as to complete the interlayer dielectric material 103. In many applications, the second layer portion is typically made up of substantially the same material as the first layer portion (e.g., silicon dioxide and the like), although other materials can be used. Accordingly, as shown in FIG. 1h, the interlayer dielectric material 103 is now made up of the material layers 103a, 112 and 103b, wherein the material of the first and second layer portions 103a, 103b (e.g., silicon dioxide) is different that of the dielectric cap layer 112 (e.g., silicon nitride).
Thereafter, when contact via openings 111 are formed in the interlayer dielectric material 103 so as to expose the source/drain regions 102d (see, FIG. 10, it will be necessary to adjust the etch recipe of the etch process 134 so as to etch the different material layers (i.e., layers 103a, 112 and 103b) of the interlayer dielectric material 103. In the event the patterned mask layer 125 is inadvertently misaligned as previously described, such that the contact via openings 111 are positioned at least partly above the gate structures 110, a portion of the dielectric cap layer 112a formed in the recesses 110r—which is made up of the same material as the cap layer 112—will potentially be affected during that portion of the etch process 134 that is adapted to etch through the cap layer 112. In such cases an upper surface 110s of one or both of the metal gate electrode materials 108 and 109 of the gate structures 110 may also be exposed, which could again potentially lead to creating a short between the gate structures 110 and the source/drain regions 102d. 
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.